Consortium

Universitat Politecnica de Catalunya

PI: Sergi Abadal (Project Coordinator)
Co-PI: Eduard Alarcón

Key Expertize: 15+ years in unconventional circuits/architectures based on 2D materials, and in model-based design space exploration and codesign methodologies, which are crucial for the unique approach of CERBERUS. On top of this, the UPC group also has experience in AI accelerator design.

Main Tasks: Within CERBERUS, the UPC group is responsible of the behavioral modeling of devices/circuits, of the establishment of the DSE framework and of the integration of models into this framework.

Chalmers University of Technology

PI: Johan Liu
Co-PI: Per Lundgren

Key Expertize: The group at Chalmers possesses pioneering experience in 2DM and molecule selection for maximum thermal performance, together with a unique setup of thermal characterization tools from nanoscale to bulk size in Myfab – the Swedish national research infrastructure for micro and nano fabrication. The group also has experience on high-speed carbon-based electronics beyond CMOS.

Main Tasks: The Chalmers group is WP3 leader for Heat Dissipation Mechanisms, and responsible to develop and optimize heat spreaders for CERBERUS’hardware.

AMO GmbH

PI: Zhenxing Wang
Co-PI: Burkay Uzlu

Key Expertize: AMO is a research foundry specialized in nanofabrication, including large area graphene integration and photovoltaics; has the necessary knowledge of semiconductor devices based on 2DMs, fabrication technology, 2DM film deposition, material and device characterization, device interface characterization, and expertise in TEM investigation of fabricated devices, among others. AMO operates the 400m2 AMICA cleanroom with the required tools to develop the work. As a deep-tech SME, AMO also brings industrial know-how and expertise in innovation and exploitation of results.

Main Tasks: AMO is responsible for fabrication and characterizing 2DM-based FETs and integrating them with memristive devices to realize 1T1R configurations.

RWTH Aachen University

Chair of Electronic Devices (ELD)

PI: Max Lemme

Key Expertize: RWTH-ELD has experience in transfer and characterization of 2D materials, as well on the development of vertical and lateral memristive devices based on 2D materials (2DMs). It works in close collaboration with the AMO team and and has full access to the AMICA cleanroom for device fabrication and characterization.

Main Tasks: Within CERBERUS, RWTH-ELD is workpackage leader of WP1, and spearheads the development of fabrication processes for monolayer 2DMs as well as the fabrication and characterization of 2DM-based memristors.

Chair of High Frequency Electronics (HFE)

PI: Renato Negra

Kex Expertize: RWTH-HFE has extensive experience in system partitioning between digital and analogue signal processing as well as in the design of innovative energy-efficient data converters , alongside the required equipment to realize them (Cadence/ADS licenses; VNA, oscilloscopes, probe stations, amplifiers, etc)

Main Tasks: RWTH-HFE leads WP2 and is responsible for the design of efficient interfaces and peripheral circuits for in-memory computing (IMC). This involves the design of analogue and mixed-signal circuits and the experimental characterisation of these circuits.

IBM Research-Zürich*

PI: Irem Boybat
Co-PI: Abbas Rahimi

Key Expertize: IBM Research-Zurich is one of the leading teams on in-memory computing (IMC) based on phase change materials. The memristive-based IMC hardware developed in Zurich is one of the most advanced in the world.

Main Tasks: As leader of WP5, IBM will carry out explorations on different parts of the software stack and explore domains, such as model partitioning, mapping, and scheduling for heterogeneous systems. IBM will also investigate the various roles of memristive devices in new emerging AI workloads, i.e. continual learning and retrieval, stochastic AI.

EPFL*

Embedded Systems Laboratory (ESL)

PI: David Atienza Alonso
Co-PI: Giovanni Ansaloni

Key Expertise: ESL expertiseinclude system-level design methodologies for high performance multi-processor system-on-chip (MPSoC) and low-power Internet-of-Things (IoT) systems, as well as hardware/software co-optimization of domain-specific architectures and algorithms.

Main Tasks: ESL will lead activities related to multi-parametric system simulation, serving as the leader for WP6.

Laboratory of Nanoscale Electronics and Structures (LANES)

PI: Andras Kis

Key Expertise: The LANES group has demonstrated the first transistor based on a 2D semiconductor and has world-leading expertise on devices and circuits based on 2D materials, including the growth of high-quality MoS2 monolayers via MOCVD.

Main Tasks: LANES will work on the 2D semiconductor growth as well as on the fabrication and characterization of memory and transistor devices based on these materials.